The present invention relates to a software analysis system for real time analysis of certain characteristics of computer programs to be run on data processing systems.
Data processing systems, which are controlled by microprocessors, execute computer programs having sometimes thousands of lines of instruction code. In more complex data processing systems the instruction code may be in the form of a high-level language such as, Pascal, FORTRAN, COBOL, or ADA as well as other high-level languages which resemble English. For each such line of high-level instruction code there may be a large number of machine-language instructions in a lower level code that are generated by the data processing systems compiler. The compiler translates high-level language commands into machine or assembly language. Each machine-language instruction has an address which corresponds to one of a plurality of possible addresses within the address space of the data processing system's microprocessor. During the execution of a particular computer program, many different addresses will be utilized and the frequency of these addresses, if known, may provide information as to how efficiently the computer program operates.
Since there may be thousands of lines of high-level instruction code needed in order to execute a particular computer program, such computer programs may not be written in the most efficient manner, thus requiring the microprocessor to execute a large number of steps when the desired operation could be accomplished with a fewer. In order to analyze the efficiency of a particular computer program, it is desirable to know which addresses within the microprocessor are being called most frequently. Clues to the operation of the program may also be derived from the timing between successive uses of certain microprocessor addresses or the frequency which with particular microprocessor address or range of addresses is called. For example, by choosing two addresses that correspond to the entry and exit points of a software subroutine, one may determine the length of time needed to execute the subroutine. It may be found that it takes longer to execute the subroutine than originally thought, thus indicating that the subroutine does not make the most efficient use of the microprocessor's time. This may lead a software engineer to redesign the program to execute the subroutine faster. It may also be important to discover whether a particular address is being called within a subroutine since the absence of that address may indicate the presence of a bug in the program.
Diagnostic test devices known generally in the industry as logic analyzers have been used in the past for debugging computer programs. A logic analyzer frequently includes a probe which is connected in parallel with the microprocessor in the system under test or "target" microprocessor to probe signals intended for the microprocessor. The logic analyzer acquires the information present on every microprocessor bus cycle and stores it in its own local memory. However, since the storage of information occurs every bus cycle and the information is in assembly language, the number of equivalent high-level language statements or events which can be stored in the memory of a logic analyzer is very small, typically less than ten or twenty for a total logic analyzer memory depth of 1000. This is due to the fact that each line of high-level language instruction code may require 10-100 bus cycles of machine code to execute it. The bus cycle information must be removed from the logic analyzer's memory to make room for new incoming information. Since the logic analyzer's events of interest occur on every bus cycle of the microprocessor, the information is stored in memory at such a high rate that it is impossible to process the information in real time. Thus, in order to analyze the data which is being stored at such a high rate of speed a logic analyzer resorts to statistical sampling. This results from the fact that the logic analyzer's random access memory (RAM) cannot store data and send for data for analysis at the same time. When the data in the logic analyzer's RAM is being read the processing takes place at a much slower rate than the incoming data. This means that large blocks of instruction code must be ignored and only samples of the program are acquired for analysis. Thus, the logic analyzer cannot acquire every single event of interest that might occur in the execution of a particular computer program.